1. Technical Field
The present invention is directed to a process for fabricating integrated vertical transistors.
2. Art Background
In integrated circuits, there is a trend toward a higher device density to increase the number of devices per unit area. Device density is increased by making individual devices smaller and placing the devices closer together. Device dimensions (termed feature size or design rules) are decreasing from 0.25 xcexcm to 0.18 xcexcm and beyond. It is also desired to decrease the distance between devices in a commensurate fashion.
Currently, most MOS (metal oxide semiconductor) transistors have a planar configuration. In a planar MOS device, the direction of the current flow is parallel to the plane of the substrate surface. Although there is a need to decrease the size of these devices to achieve increased device density, fabricating these small devices becomes increasingly difficult. In particular, lithography becomes extremely difficult as device dimensions decrease to less than the wavelength of the radiation used to delineate an image of a pattern in a radiation-sensitive material.
A vertical device configuration, described in Takato, H., et al., xe2x80x9cImpact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI""sxe2x80x9d IEEE Transactions on Electron Devices, Vol. 38 (3), pp. 573-577 (1991) has been proposed as an alternative to the more space-consuming planar device configuration. A schematic of the device is illustrated in FIG. 1. The device 10 has a source 15, drain 20, and channel 25. The length of the channel 25 is perpendicular to the surface of the substrate 30 on which the device 10 is formed. The device is called a vertical transistor because the length of the channel is perpendicular to the substrate surface. A gate 35 surrounds the channel 25.
Although vertical MOSFETs (metal oxide semiconductor field effect transistors) can be packed more densely than planar MOSFETs, the processing issues for the vertical transistors are not trivial. The problems associated with vertical transistor fabrication are exacerbated for complementary MOS technologies (CMOS) in which both n-type and p-type devices are fabricated on a single substrate. A process that makes it easier and more efficient to fabricate vertical MOSFETs for CMOS applications is therefore desired.
The present invention is directed to a process for fabricating integrated n-MOS and p-MOS vertical transistors for CMOS applications. In the process, n-MOS and p-MOS devices are formed on a semiconductor substrate. The semiconductor substrate is any suitable crystalline semiconductor substrate or silicon on insulator substrate. The substrate is either an unprocessed (bare) wafer or a substrate which has already had one or more device layers formed thereon or has otherwise been previously processed.
In the process, the device active regions (i.e. the source extension, the drain extension, and channel) are defined by depositing at least three layers of material on the substrate. The first and third of these layers are used to define one of either a source or drain extension in a plug of semiconductor material subsequently formed in the three layers of material. Whether the first layer is used to form a source or drain extensions depends on whether the device source or the device drain is formed under the semiconductor plug. That is, if the device source is formed under the semiconductor plug, then the first layer is used to define the source extension and the third layer is used to define the drain extension. If the device drain is formed beneath the semiconductor plug, then the first layer is used to define the drain extension and the third layer is used to define the source extension.
The n-MOS and p-MOS devices are formed by defining two regions in the substrate. Substrate, as used herein, is the semiconductor substrate at the relevant point in the process sequence (i.e. including the materials formed on the semiconductor substrate). The first region is the region in which the n-MOS devices are subsequently formed. The first region is therefore selectively implanted with an n-type dopant (e.g. arsenic or phosphorus). At least two implants are required to dope both the first and third layers as well as the source or drain. The second region is the region in which the p-MOS devices are formed. The second region is therefore selectively implanted with a p-type dopant (e.g. boron). Again, at least two implants are needed to dope both the first and third layers as well as the device source or drain.
The depth of the implant peak and dose of these implants is selected to provide a certain threshold concentration (e.g. greater than 1xc3x971019/cm3 for the source and drain and greater than 1xc3x971020/cm3 for the dopant sources for the source and drain extensions). For convenience, the source (drain) is distinguished from the source (drain) extension by referring to it as the deep source (drain). The depth of the first implant peak is near the surface of the underlying semiconductor substrate. Dopant at this depth is used to define one of either the deep source or deep drain of the device. The second depth is the first layer of material formed on the semiconductor substrate. Dopant in this layer is used to form the applicable source/drain extension. The third depth is the third layer formed on the semiconductor substrate. Dopant in this layer is used to form the other source/drain extension. The dopants are implanted instead of introduced in-situ because different dopants are required depending upon whether the device being formed is n-MOS or p-MOS. In an alternate embodiment, the first and third layers are selectively implanted immediately after each layer is respectively formed on the substrate.
The n-type region is electrically isolated from the p-type regions by forming a trench in the semiconductor substrate. The trench is then filled with a dielectric material. The point in the process sequence when this electrical isolation is performed is largely a matter of design choice.
After the n-MOS and p-MOS regions are formed, windows are formed in the at least three layers of material formed on the substrate. The windows terminate at or slightly below the surface of the underlying semiconductor substrate. The windows are then filled with a semiconductor material.
The source/drain extensions and the channel of the device are formed in this plug of semiconductor material. If the plug is formed in the n-type region, the device formed in that region will be an n-MOS device. If the plug is formed in the p-type region, the resulting device will be a p-MOS device. The device regions are formed using a combination of selective implants and the introduction of dopants from the adjacent doped layers of material. The device has self-aligned source and drain extensions in that the thicknesses of the first and third layers of doped material define the source and drain extensions in the semiconductor plug and the second layer holds the place for the subsequently formed gate. The thickness of the second layer of material defines the gate length of the device.
Thin (i.e. about 50 nm or less) layers of material are formed between the first, second, and third layers. The material for these layers is selected to have a higher degree of resistance to the etch expedients selected to remove some or all of the three material layers. These expedients are referred to as etchants. These thin layers are referred to as etch stop layers. These thin layers are also used to define the relative spacing of the device gate and the source and drain extensions.
The second layer of material is sacrificial (i.e. no portion of it is present in the formed device). When the second layer is removed, a portion of the surface of the adjacent semiconductor plug is exposed. A gate dielectric material is then formed on the exposed portion of the semiconductor plug using conventional expedients.
The gate is then formed on the substrate. In the embodiment of the present invention wherein the gate material for the n-type devices is the same as the gate material for the p-type devices, the gate material is simply deposited and patterned.
In the embodiment of the present invention wherein the gate material for the n-type devices is different than the gate material for the p-type devices, the second layer of material is removed selectively from either the n-type or p-type region. For example, the second layer of material for the n-type devices is removed while the p-type region is masked. While the p-type devices are masked, the n-type region is implanted with dopants as desired, after which the second layer in the n-type region is removed. The gate dielectric is then formed on the exposed portion of the semiconductor plug in the n-type region, after which a conductive layer of a first gate material is formed on the entire substrate (the mask over the p-type device regions having previously been removed). The first gate material (e.g. polycrystalline silicon doped with n-type dopants) is then selectively removed, and the only portion that remains is the portion adjacent to the semiconductor plug of the n-type devices. The selective process of second layer removal, gate dielectric formation and second gate material deposition is then performed for the p-type region.
Electrical interconnects are then formed on the substrate. In this embodiment, the conductive gate material for the p-type devices is electrically connected to the conductive gate material for the n-type devices. This is referred to as a strap connection. This contact is in addition to any desired interconnects formed between the gate electrodes and the substrate regions having devices of either polarity. Consequently, in this embodiment, a conductive material is deposited and patterned to form these two interconnects.